Selectable trim settings on a memory device

ABSTRACT

The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.

PRIORITY INFORMATION

This application is a continuation of U.S. application Ser. No. 15/802,521, filed on Nov. 3, 2017, the contents of which are incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to memory systems, and more particularly, to apparatuses and methods with selectable trim settings on a memory device.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and can include random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, among others.

Memory devices can be utilized as volatile and non-volatile memory for a wide range of electronic applications in need of high memory densities, high reliability, and low power consumption. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, and movie players, among other electronic devices.

Resistance variable memory devices can include resistive memory cells that can store data based on the resistance state of a storage element (e.g., a resistive memory element having a variable resistance). As such, resistive memory cells can be programmed to store data corresponding to a target data state by varying the resistance level of the resistive memory element. Resistive memory cells can be programmed to a target data state (e.g., corresponding to a particular resistance state) by applying sources of an electrical field or energy, such as positive or negative electrical pulses (e.g., positive or negative voltage or current pulses) to the cells (e.g., to the resistive memory element of the cells) for a particular duration. A state of a resistive memory cell can be determined by sensing current through the cell responsive to an applied interrogation voltage. The sensed current, which varies based on the resistance level of the cell, can indicate the state of the cell.

One of a number of data states (e.g., resistance states) can be set for a resistive memory cell. For example, a single level memory cell (SLC) can be programmed to a targeted one of two different data states, which can be represented by the binary units 1 or 0 and can depend on whether the cell is programmed to a resistance above or below a particular level. As an additional example, some resistive memory cells can be programmed to a targeted one of more than two data states (e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110). Such cells may be referred to as multi state memory cells, multiunit cells, or multilevel cells (MLCs). MLCs can provide higher density memories without increasing the number of memory cells since each cell can represent more than one digit (e.g., more than one bit).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a system including an apparatus in the form of a computing device and an apparatus in the form of a memory device in accordance with one or more embodiments of the present disclosure.

FIG. 2 is a block diagram of host commutatively coupled to a system including an apparatus in the form of a computing device and an apparatus in the form of a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 3 is a diagram including a table illustrating a number of trim setting configurations for a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 4 is a diagram including tables with trim setting parameters associated with operational characteristics of a memory device in accordance with a number of embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.

In a number of embodiments, a controller can include a number of sets of trims settings (e.g. trim setting configurations) that can be used by a memory device. One of the number of sets of trim settings can be selected for a particular memory device coupled to the controller. The particular memory device can operate using the selected set of trim settings and have the operational characteristics associated with the selected set of trim settings.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators “M”, “N”, and “X”, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included. As used herein, “a number of” a particular thing can refer to one or more of such things (e.g., a number of memory devices can refer to one or more memory devices).

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 120 may reference element “20” in FIG. 1, and a similar element may be referenced as 220 in FIG. 2. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure.

FIG. 1 is a block diagram of a system 100 including an apparatus in the form of a computing device 102 and an apparatus in the form of a memory device 110 in accordance with one or more embodiments of the present disclosure. As used herein, an “apparatus” can refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuitry, a die or dice, a module or modules, a device or devices, or a system or systems, for example. In the embodiment illustrated in FIG. 1, system 100 can include a computing device 102, with controller 104, and memory device 110. The computing device 102 and the memory device 110 can communicate via communication channel 108. Memory device 110 can include array 112, which can include volatile memory and/or non-volatile memory.

Controller 104 and/or a controller on memory device 110 can include control circuitry, e.g., hardware, firmware, and/or software. In one or more embodiments, controller 104 and/or a controller on memory device 110 can be an application specific integrated circuit (ASIC) coupled to a printed circuit board including a physical interface.

Memory device 110 can provide main memory for system 100 or could be used as additional memory or storage throughout system 100. System 100 can include memory device 110 and/or a number of memory devices, where each memory device can include one or more arrays of memory cells 112, e.g., non-volatile and/or volatile memory cells. The arrays can be flash arrays with a NAND architecture, for example. Embodiments are not limited to a particular type of memory device. For instance, the memory device can include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and/or flash memory, among others.

The embodiment of FIG. 1 can include additional circuitry that is not illustrated so as not to obscure embodiments of the present disclosure. For example, the system 100 can include address circuitry to latch address signals provided over I/O connections through I/O circuitry. Address signals can be received and decoded by a row decoder and a column decoder to access the memory device 110. It will be appreciated by those skilled in the art that the number of address input connections can depend on the density and architecture of the memory device 110.

In a number of embodiments, trims that control the performance of the memory device 110 are located on the memory device 110. Controller 104 can include registers, buffers, and/or memory to store trim settings 106 that define the trims for the data in memory device 110. Trim settings 106 can also be stored in the memory device 110. Trim settings 106 can include a number of parameters that can control the operation and performance of the memory device. For example, the trim settings can include parameters such as the programming signal magnitude (e.g., voltage and/or current level), erase signal magnitude (e.g., voltage and/or current level), sensing signal magnitude (e.g., voltage and/or current level), programming signal length, erase signal length, sensing signal length, number of bits per cells, number of programming signals in a programming operation, number of sensing signals in a sensing operation, and/or allowable programming operation rate for a memory device. Trim settings can include a number of settings for each of the number of parameters.

The trim settings can control the operational characteristics of the memory device 110. The operational characteristics of the memory device can include life span of the memory device 110, data retention characteristics for the data in the memory device 110, the storage density (e.g., the number of bits stored) for the memory device 110, disturb characteristics for the data in the memory device 110, programming speed for the memory device 110, power consumption for the memory device 110, sensing speed for the memory device 110, operation temperature for the memory device 110, and/or programming operation rate for the memory device 110, among other operational characteristics.

In a number of embodiments, trim settings 106 can include a number of configurations of trim setting parameters that can control the operational characteristics of the memory device 110. A trim setting configuration can include setting each of the number of trim setting parameters at particular levels to provide particular operational characteristics for memory device 110. A particular trim setting configuration can be associated with particular operational characteristics for a memory device. A trim setting configuration used to operate memory device 110 can be based on desired operational characteristics 120 for memory device 110, die info for the array 112, and/or metadata for the data in memory device 110.

Trim settings 106 on controller 104 can include a look up table that includes a number of trim setting configurations. A particular trim setting configuration of the number of trim setting configurations in trim settings 106 can be sent to memory device 110 and used by memory device 110 during operation to provide operational characteristics for memory device 110 associated with the particular trim setting configuration. A trim setting configuration used by memory device 110 can control the operational characteristics of memory device 110 such that memory device 110 can perform with desired operational characteristics.

The operational characteristics of memory device 110 can be controlled by the trim setting parameters in trims settings 106. For example, the operational characteristic of life span for memory device 110 can be dependent on trim setting parameters such as the allowable programming operation rate and programming signal magnitude, for example. The life span of memory device 110 can be dependent on the allowable programming operation rate (e.g., the number of programming operations performed over a period of time) and the programming signal magnitude because a memory device has a finite number of times the memory cells of the memory device can be programmed before the memory cells fail, which in turn can be dependent on the magnitude of the programming signal used to program the memory cells. Therefore, the trim setting parameters for memory device 110 can include setting the allowable programming operation rate at a particular number of programming operations per minute to allow the memory device to have a particular life span based on prior operational characteristics of the memory device, prior trim setting configurations used by the memory device, and/or desired operational characteristics of the memory device.

In FIG. 1, trim settings 106 can include trim setting 1 (TS-1) 109-1, trim setting 2 (TS-2) 109-2, and trim setting N (TS-N) 109-N. Trim setting 109-1 can be associated with memory device 100 operating with a first group of operational characteristics, trim setting 109-1 can be associated with memory device 100 operating with a second group of operational characteristics, and trim setting 109-N can be associated with memory device 100 operating with an Nth group of operational characteristics. One of the trim settings 109-1, 109-2, and 109-N can be selected and sent to memory device 110 based on the desired operational characteristics for memory device 110.

FIG. 2 is a block diagram of host 201 commutatively coupled to a system 200 including an apparatus in the form of a computing device 202 and an apparatus in the form of a memory device 210 in accordance with a number of embodiments of the present disclosure. Host 201 can send a selection signal (SS) 211 to the controller of computing device 202 to select a trim setting configuration for memory device 210. Selection signal 211 can select one of a number trim setting configurations stored on computing device 202 (e.g., trim setting configurations 109-1, 109-2, and 109-N in FIG. 1 or trim setting configurations 309-1, 309-2, and 309-N in FIG. 3). The memory device 210 can operate using the selected trim setting configuration and, then in turn, have the operational characteristics associated with the selected trim setting configuration.

FIG. 3 is a diagram including a table illustrating a number of trim setting configurations for a memory device in accordance with a number of embodiments of the present disclosure. In FIG. 3, trim setting configurations 309-1, 309-2, and 309-N can include the trim setting parameters programming signal magnitude 370, sensing signal magnitude 371, erase signal magnitude 372, programming signal length 373, erase signal length 374, sensing signal length 375, number of bits per cell 376, number of programming signals in a programming operation 377, number of sensing signals in a sensing operation 378, and allowable programming operation rate 379. In a number of embodiments, one of the number of trim setting configurations 309-1, 309-2, and 309-N can be selected for the memory device and/or devices. The selected trim setting configuration can be sent to the memory device and/or memory device.

In FIG. 3, trim setting 1 309-1 can include programming signal magnitude 370 at level 2, sensing signal magnitude 371 at level 2, erase signal magnitude 372 at level 2, programming signal length 373 at level 2, erase signal length 374 at level 2, sensing signal length 375 at level 2, number of bits per cell 376 at 1 bit per memory cell, number of programming signals in a programming operation 377 at 1 programming signal per programming operation, number of sensing signals in a sensing operation 378 at 1 sensing signal per sensing operation, and allowable programming operation rate 379 at 100 programming operations per minute.

Trim setting 1 309-1 can be selected for a memory device that is used to store static and/or dynamic data that can be programmed and sensed in a variety of environments. The programming signal magnitude 370, sensing signal magnitude 371, erase signal magnitude 372, programming signal length 373, erase signal length 374, sensing signal length 375 are all at level 2 such that the signals provide data retention and disturb characteristics, refresh operations, and/or replacement indications for a variety of operation conditions. The number of bits per memory cell is 1 bit per memory cells so the memory cells can be programmed with only 1 programming signal, which can allow memory cells to be programmed quicker and with less power when compared to memory cells programmed with more bits and signals. For example, a controller can send data to a portion of the memory device that is using trim setting 1 309-1 where the data has characteristics that are suited to for operations, such as reading and/or writing the data, using the trim settings of trim setting 1 309-1.

In FIG. 3, trim setting 1 309-2 can include programming signal magnitude 370 at level 3, sensing signal magnitude 371 at level 3, erase signal magnitude 372 at level 3, programming signal length 373 at level 3, erase signal length 374 at level 3, sensing signal length 375 at level 3, number of bits per cell 376 at 3 bits per memory cell, number of programming signals in a programming operation 377 at 3 programming signals per programming operation, number of sensing signals in a sensing operation 378 at 1 sensing signal per sensing operation, and allowable programming operation rate 379 at 20 programming operations per minute.

Trim setting 2 309-2 can be selected for a memory device that is used to store static data that will be stored on the memory device without being updated frequently and can be retained in a variety of environments. The programming signal magnitude 370, sensing signal magnitude 371, erase signal magnitude 372, programming signal length 373, erase signal length 374, sensing signal length 375 are all at level 3 such that the signals provide data retention, disturb characteristics, refresh operations, and/or replacement indications for a variety of more extreme of operation conditions (e.g., temperature variation between programming operations and sensing operations). The number of bits per memory cell is 3 bits per memory cells and the memory cells can be programmed with 3 programming signal, which can allow the data in the memory cells to be stable.

In FIG. 3, trim setting 1 309-N can include programming signal magnitude 370 at level 1, sensing signal magnitude 371 at level 1, erase signal magnitude 372 at level 1, programming signal length 373 at level 1, erase signal length 374 at level 1, sensing signal length 375 at level 1, number of bits per cell 376 at 3 bits per memory cell, number of programming signals in a programming operation 377 at 1 programming signal per programming operation, number of sensing signals in a sensing operation 378 at 1 sensing signal per sensing operation, and allowable programming operation rate 379 at 500 programming operations per minute.

Trim setting N 309-N can be selected for a memory device that is used to store dynamic data that will be stored on the memory device for shorter periods of time and/or be updated frequently. The programming signal magnitude 370, sensing signal magnitude 371, erase signal magnitude 372, programming signal length 373, erase signal length 374, sensing signal length 375 are all at level 1 such that the signals provide programming speed and sensing speed to write and access data more frequently than data that is to be retained for longer periods of time. The number of bits per memory cell is 3 bits per memory cells so the storage capacity of the memory device is higher than storing 1 bit per memory cell and the memory cells can be programmed with 1 programming signal which allows data to be programmed quickly but have reduced data retention characteristics.

FIG. 4 is a diagram including tables with trim setting parameters associated with operational characteristics of a memory device in accordance with a number of embodiments of the present disclosure. In FIG. 4, the operational characteristics of a memory device include life span 461, data retention 462, storage density 463, disturb characteristics 464, programming speed 465, power consumption 466, sensing speed 467, and temperature 468. The operational characteristics in FIG. 4, among other operational characteristics, can be affected and/or controlled by trim setting parameters. In FIG. 4, the trim setting parameters associated with operational characteristics of a memory device include programming signal magnitude 470, sensing signal magnitude 471, erase signal magnitude 472, programming signal length 473, erase signal length 474, sensing signal length 475, number of bits per cell 476, number of programming signals in a programming operation 477, number of sensing signals in a sensing operation 478, and allowable programming operation rate 479. Embodiments of the present disclosure are not limited to the trim setting parameters in FIG. 4 and can include other trim setting parameters that are associated with operational characteristics of a memory device.

In FIG. 4, life span 461 of a memory device can be associated with the allowable programming operation rate 479, the programming signal magnitude 471, and programming signal length. Memory cells of memory devices can be programmed a finite number of times before they will fail. The number of times memory cells can be programmed is also associated with the magnitude and duration of the programming signals used to the program the memory cells. Trim setting configurations can include setting an allowable programming operation rate 479, along with the programming signal magnitude 471 and programming signal length to affect the life span 461 of the memory device.

In FIG. 4, data retention 462 in a memory device can be associated with the programming signal magnitude 471 and programming signal length. Data retention 462 in a memory device is the length of time after memory cells are programmed that bits of data stored in memory cells can be read without error. The magnitude of the programming signal and the length that the programming signal is applied to the memory cells can affect the data retention 462 characteristics of a memory device. For example, the voltage of the programming signal can be a particular magnitude such that the memory cell can be read over a period time despite voltage drift and/or disturb affecting reading of the data in the memory cells. Also, the length of the programming signal can be associated ensuring that programming operations are programming memory cells to the desired voltage to have desired data retention characteristics. Trim setting configurations can include setting the programming signal magnitude 471 and programming signal length 473 to affect data retention 462 characteristics in a memory device.

In FIG. 4, storage density 463 of a memory device can be associated with the number of bits per cell 476 and the number of programming signals in a programming operation 477. Storage density 463 of a memory device can include the number of bits stored per memory cell. A first portion of a memory device can store a first number of bits per memory cell and a second portion of a memory device can store a second number of bits per memory cell. Trim setting configurations that include setting the storage density 463 of a memory device can affect the programming speed of a memory device, the amount of data that can be stored on a memory device, and/or the power consumption of memory device, among other operational characteristics of a memory device. A memory device can include trim setting configurations that include the number of bits per memory cell 476 and the number of programming signals in a programming operation 477 to affect the storage density 463 of a memory device.

In FIG. 4, disturb 464 characteristics of a memory device can be associated with programming signal magnitude 470, sensing signal magnitude 471, erase signal magnitude 472, programming signal length 473, erase signal length, 474, sensing signal length 475, number of sensing signals in a sensing operation 478, number of programming signals in a programming operation 477, and number of bits per memory cell 476. Memory cells can be affected by other memory cells in a memory device. For example, the voltage of memory cell and how it was programmed to that voltage can affect the voltage of other memory cells. Also, how memory cells are sense and/or erased can affect the voltage of other memory cells. The effects of memory cells on each other in memory devices can be referred to as disturb characteristics 464 of the memory device due memory cells disturbing other memory cells. A memory device can include trim setting configurations that include the programming signal magnitude 470, the sensing signal magnitude 471, the erase signal magnitude 472, the programming signal length 473, the erase signal length, 474, the sensing signal length 475, the number of sensing signals in a sensing operation 478, the number of programming signals in a programming operation 477, and the number of bits per memory cell 476 of a memory device to affect the disturb 464 characteristics of a memory device.

In FIG. 4, programming speed 465 of a memory device can be associated with the number of programming signals in a programming operation 477, allowable programming operation rate 479, programming signal magnitude 470, and the programming signal length 473. Trim setting configurations that include setting the programming speed 465 of a memory device can affect data retention in a memory device, the life span of a memory device, and/or the power consumption of memory device, among other operational characteristics of a memory device. A memory device can include trim setting configurations that include the number of programming signals in a programming operation 477, the allowable programming operation rate 479, the programming signal magnitude 470, and the programming signal length 473 to affect the programming speed 465 of a memory device.

In FIG. 4, power consumption 466 of a memory device can be associated with programming signal magnitude 470, sensing signal magnitude 471, erase signal magnitude 472, programming signal length 473, erase signal length, 474, sensing signal length 475, number of sensing signals in a sensing operation 478, and number of programming signals in a programming operation 477. Power consumption of 466 of a memory device can be affected by the voltage level that is being used to program, erase, and sense the memory cells, along with the duration and number of signals that are being used to program, erase, and sense the memory cells. A memory device can include trim setting configurations that include the programming signal magnitude 470, the sensing signal magnitude 471, the erase signal magnitude 472, the programming signal length 473, the erase signal length, 474, the sensing signal length 475, the number of sensing signals in a sensing operation 478, the number of programming signals in a programming operation 477, of a memory device to affect the power consumption 466 of a memory device.

In FIG. 4, sensing speed 467 of a memory device can be associated with the number of sensing signals in a sensing operation 478, the sensing signal magnitude 471, and the sensing signal length 475. Trim setting configurations that include setting the sensing speed 467 of a memory device can affect the latency associated with performing read operations on a memory device. A memory device can include trim setting configurations that include the number of sensing signals in a sensing operation 478, the sensing signal magnitude 471, and the sensing signal length 475 to affect the sensing speed 467 of a memory device.

In FIG. 4, the temperature 468 of a memory device can be associated with programming signal magnitude 470, sensing signal magnitude 471, erase signal magnitude 472, programming signal length 473, erase signal length, 474, sensing signal length 475, number of sensing signals in a sensing operation 478, and number of programming signals in a programming operation 477. Memory cells can be affected by the temperature of memory device. For example, the temperature of memory device when memory cells are programmed and/or read can affect the signals used to program, erase, and sense the memory cells. Also, temperature of a memory device when data is programmed and/or read can affect data retention characteristics, the programming speed, sensing speed, power consumption, and life span of a memory device. A memory device can include trim setting configurations that include the programming signal magnitude 470, the sensing signal magnitude 471, the erase signal magnitude 472, the programming signal length 473, the erase signal length, 474, the sensing signal length 475, the number of sensing signals in a sensing operation 478, and the number of programming signals in a programming operation 477 of a memory device to account for the temperature 468 of a memory device.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. 

What is claimed is:
 1. An apparatus, comprising: an array of memory cells; and a controller, wherein the controller is coupled to the array of memory cells and includes control circuitry configured to: store a number of sets of trim settings, wherein the number of sets of trim settings are each configured to provide particular operational characteristics for the array of memory cells; and select a particular set of trims settings of the number of sets of trim settings including particular trim setting parameters based on desired operational characteristics for the array of memory cells.
 2. The apparatus of claim 1, wherein the operational characteristics include programming operation speed for the array of memory cells.
 3. The apparatus of claim 1, wherein the operational characteristics include life span for the array of memory cells.
 4. The apparatus of claim 1, wherein the operational characteristics include data retention characteristics for the array of memory cells.
 5. The apparatus of claim 1, wherein the operational characteristics include storage density characteristics for the array of memory cells.
 6. The apparatus of claim 1, the particular set of trim settings is selected by a host.
 7. An apparatus, comprising: an array of memory cells; and a controller, wherein the controller is coupled to the array of memory cells and includes control circuitry configured to: operate the array of memory cells using a particular set of trims settings, including particular trim setting parameters, selected based on desired operational characteristics for the array of memory cells, wherein the particular trim setting parameters include a number of bits per cell.
 8. The apparatus of claim 7, wherein the particular set of trim settings are selected from a number of sets of trim settings based on the desired operational characteristics associated with the particular set of trim settings.
 9. The apparatus of claim 7, wherein the particular set of trim settings are configured to provide desired data retention characteristics for static data.
 10. The apparatus of claim 7, wherein the particular set of trim settings are configured to provide desired programming speed characteristics for dynamic data.
 11. The apparatus of claim 7, wherein the particular set of trim setting are selected from a group of sets of trim settings stored as a look up table in the controller.
 12. The apparatus of claim 7, wherein the particular set of trim settings include a particular number of programming signals in a programming operation to manage storage density of the memory device.
 13. The apparatus of claim 7, wherein the particular set of trim settings include a particular number of programming signals in a programming operation, a particular allowable programming operation rate, a particular programming signal magnitude, and a particular programming signal length to manage a programming speed of the memory device.
 14. The apparatus of claim 7, wherein the particular set of trim settings include a particular number of sensing signals in a sensing operation, a particular sensing signal magnitude, a particular sensing signal length to manage a sensing speed of the memory device.
 15. A method, comprising: selecting a set of trim settings, including trim setting parameters, for a memory device from a group of sets of trim settings based on desired operational characteristics of the memory device for how the memory device will be used.
 16. The method of claim 15, furthering including selecting the set of trim settings based on where the memory device will be used.
 17. The method of claim 15, furthering including selecting the set of trim settings based on desired power consumption for the memory device.
 18. The method of claim 15, further including selecting the set of trim settings with a particular allowable programming operation rate, a particular programming signal magnitude, and a particular programming signal length to manage a life span of the memory device.
 19. The method of claim 15, further including selecting the set of trim settings with a particular programming signal magnitude and a particular programming signal length to manage data retention characteristics of the memory device.
 20. The method of claim 15, further including selecting the set of trim settings with a particular programming signal magnitude, a particular sensing signal magnitude, a particular erase signal magnitude, a particular programming signal length, a particular erase signal length, a particular sensing signal length, a particular number of sensing signals in a sensing operation, a particular number of programming signals in a programming operation, and a particular number of bits per memory cell to manage disturb characteristics of the memory device. 